Semiconductor Research Corporation and UCLA Advance Design-Dependent Process Monitoring for Semiconductor Wafer Manufacturing

University of California - Los Angeles(UCLA)
June 1, 2011

Research Promises Semiconductor Manufacturing Cost and Production Savings Up to 15 Percent, Potentially Increasing Profit Per Chip Significantly.

Semiconductor Research Corporation (SRC), the world's leading university-research consortium for semiconductors and related technologies, and researchers from the UCLA Henry Samueli School of Engineering and Applied Science have developed a new method of design-dependent process monitoring for semiconductor wafer manufacturing. The advance promises to provide semiconductor chip manufacturing cost and productivity savings up to 15 percent, potentially increase profit per chip by as much as 12 percent and ultimately lead to less expensive and higher performing electronics devices.

The complexities of semiconductor manufacturing and the challenges of keeping pace with Moore’s Law are well known within the industry. Modern manufactured chips exhibit wide power and performance variation that necessitate careful screening, and frequency and power tests to screen for defective chips after chip packaging has been completed are expensive and time consuming.

Therefore, the industry has significant incentive to prune failed wafers and chips during early stages of manufacturing wherever possible. While increased attention has been given to the design-manufacturing interface, little has been done to drive design intent into manufacturing.

That’s where UCLA Engineering research comes into play. By using process monitors on wafer lines tested after the initial manufacturing steps, manufacturers would be able to evaluate early die performance and wafer yield estimation. Avoiding going through all the manufacturing steps for a bad wafer can realize the significant cost savings. Avoiding testing failed die later in the process by leveraging the pruning approach is expected to save manufacturing costs further, with nearly 70 percent of failed chips pruned with less than a 1 percent yield loss. Though the results will depend on the design as well as the manufacturing process, the approach is especially useful in early stages of yield ramp for a product. An early version of this work appeared in the International Conference on Computer-Aided Design in 2010.
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