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Thursday, 14 July 2011

Applied Materials Pushes the Boundaries of the Transistor with Atomic Scale Manufacturing Technology

Applied Materials
July 12, 2011

  • At 22nm, the heart of the transistor gate - its dielectric film stack - must be atomically engineered
  • Challenge: Forming atomically thin film stacks with clean, precisely-controlled interfaces
  • Solution: Performing multiple process steps, including advanced high-k ALD technology, entirely under vacuum
Applied Materials, Inc. today launched its Applied Centura® Integrated Gate StackTM system for creating the critical gate dielectric structures in 22nm logic chips. This system is the only tool available that can process the entire high-k multilayer stack in a single vacuum environment, thus preserving the integrity of its critical film interfaces. This capability is vital to maximizing transistor speed and minimizing power consumption in leading-edge microprocessor and graphics chips.

As logic chips scale down to the 22nm node and beyond, the heart of the transistor gate structure, its dielectric film stack, is becoming so thin that it must be atomically engineered. To meet this challenge, the Integrated Gate Stack system features Applied's advanced atomic layer deposition (ALD) technology, which builds ultra-thin, hafnium-based layers less than 2nm in thickness - about one hundred thousandth the width of a human hair - a fraction of a monolayer at a time, with unmatched uniformity across the wafer.

More importantly, as these films become thinner, the interfaces between adjacent layers become more crucial. The new Integrated Gate Stack system fabricates the entire gate dielectric gate stack - involving typically four process steps - entirely under vacuum. This unique approach avoids contamination of the interfaces from exposure to ambient air which can degrade transistor performance. Applied's researchers have found that eliminating air exposure during processing offers a significant performance boost: mobility in the transistor can improve by up to 10% and switching voltage variability between transistors can be reduced by up to 40%, enabling the manufacture of faster, higher-value chips.
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